Method for manufacturing semiconductor device

ABSTRACT

An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a semiconductor device in which an oxide semiconductor is used.

2. Description of the Related Art

In recent years, a technique for forming a thin film transistor (also referred to as a TFT) using an oxide semiconductor and applying the thin film transistor to an electron device and the like has attracted attention. For example, a technique for forming a switching element of an image display device and the like using zinc oxide or an In—Ga—Zn—O based oxide semiconductor as an oxide semiconductor film is disclosed in Patent Document 1 and Patent Document 2.

Etching treatment is a typical technique for processing an oxide semiconductor (see Patent Document 3 and Patent Document 4); however, there are problem. For example, wet etching is unsuitable for miniaturization of an element since wet etching is isotropic etching. In addition, since a chemical solution is used in wet etching, there is a disadvantage in controllability. On the other hand, dry etching has advantages of miniaturization and controllability; however, there is a disadvantage in that an etching rate is small, so that it takes much time to perform treatment. In addition, there is a possibility that variation occurs in a surface to be etched depending on a device used.

REFERENCE

[Patent Document 1] Japanese Published Patent Application No. 2007-123861.

[Patent Document 2] Japanese Published Patent Application No. 2007-96055.

[Patent Document 3] Japanese Published Patent Application No. 2008-41695

[Patent Document 4] Japanese Published Patent Application No. 2008-42067.

SUMMARY OF THE INVENTION

In this manner, some techniques for processing an oxide semiconductor have already existed. However, a processing technique which satisfies conditions required for manufacturing a semiconductor device with the use of an oxide semiconductor has not been established yet.

Further, a rare metal such as indium is used for an oxide semiconductor. In a conventional processing technique including etching, the major portion of an oxide semiconductor layer including such an expensive metal which is deposited is removed and wasted. Therefore, it is difficult to reduce a cost for manufacturing a semiconductor device in which an oxide semiconductor is used by the conventional processing technique. In addition, measure against problems in resource saving is required.

In view of the aforementioned problems, an object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. Further, another object is to provide a method for manufacturing a semiconductor device useful for the resource saving.

According to one embodiment of the present invention, an island-shaped oxide semiconductor layer functioning as an active layer and a conductive layer covering the island-shaped oxide semiconductor layer are processed by dry etching using a gas including chlorine and oxygen. For example, the conductive layer is processed by dry etching to form a source electrode and a drain electrode, and part of the oxide semiconductor layer is removed by the dry etching to form a recessed portion in the island-shaped oxide semiconductor layer. At this time, a gate insulating layer located below the island-shaped oxide semiconductor layer is preferably formed using a material including silicon oxide.

Alternatively, an oxide semiconductor layer over the gate insulating layer is processed by wet etching so as to be the island-shaped oxide semiconductor layer.

Details thereof are described below.

According to an embodiment of the present invention disclosed, a gate electrode is formed over a substrate; a gate insulating layer is formed over the gate electrode; an oxide semiconductor layer is formed over the gate insulating layer; the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer; a conductive layer covering the island-shaped oxide semiconductor layer is formed; the conductive layer is processed by first dry etching to form a source electrode and a drain electrode and a part of the island-shaped oxide semiconductor layer is removed by second dry etching to form a recessed portion in the island-shaped oxide semiconductor layer, or the conductive layer is processed by dry etching to form a source electrode and a drain electrode and a part of the island-shaped oxide semiconductor layer is removed by the dry etching.

According to another embodiment of the present invention disclosed, a gate electrode is formed over a substrate; a gate insulating layer is formed over the gate electrode; a first oxide semiconductor layer is formed over the gate insulating layer; a second oxide semiconductor layer whose conductivity is higher than a conductivity of the first oxide semiconductor layer is formed over the first oxide semiconductor layer; the first oxide semiconductor layer and the second oxide semiconductor layer are processed by wet etching to form a first island-shaped oxide semiconductor layer and a second island-shaped oxide semiconductor layer; a conductive layer is formed to cover the second island-shaped oxide semiconductor layer; the conductive layer is processed by first dry etching to form a source electrode and a drain electrode and a part of the first island-shaped oxide semiconductor layer and a part of the second island-shaped oxide semiconductor layer are removed by second dry etching to form a recessed portion in the first island-shaped oxide semiconductor layer, or the conductive layer is processed by dry etching to form a source electrode and a drain electrode and a part of the first island-shaped oxide semiconductor layer and a part of the second island-shaped oxide semiconductor layer are removed by the dry etching to form a recessed portion in the first island-shaped oxide semiconductor layer.

In the above description, the oxide semiconductor layer (including the first oxide semiconductor layer and the second oxide semiconductor layer) may include indium, gallium, and zinc. In addition, the conductive layer can be formed using a material whose etching rate in the dry etching is higher than that of a material used for the oxide semiconductor layer (including the first oxide semiconductor layer and the second oxide semiconductor layer).

The above dry etching can be performed using a gas including chlorine. In this case, a material including silicon oxide is preferably used for the gate insulating layer and the gas including chlorine preferably includes oxygen. Further, the content of the oxygen in the gas including chlorine may be 15 volume % or more.

Further, a metal element as can be collected from a wasted solution obtained after wet etching.

According to another embodiment of the present invention disclosed, a gate electrode is formed over a substrate; a gate insulating layer is formed over the gate electrode; an island-shaped oxide semiconductor layer is formed over the gate insulating layer; a conductive layer is formed to cover the island-shaped oxide semiconductor layer; the conductive layer is processed by dry etching using a gas including chlorine and oxygen to form a source electrode and a drain electrode and (at the same time) part of the oxide semiconductor layer is removed by the dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

In the above description, the oxide semiconductor layer may include indium, gallium, and zinc. In addition, the conductive layer can be formed using a material whose etching rate in the dry etching is higher than that of a material used for the oxide semiconductor layer. A material including silicon oxide is preferably used for the gate insulating layer. The content of the oxygen in the gas including chlorine and oxygen may be 15 volume % or more

Note that “etching rate” refers to an amount of a film which is etched per unit time (an amount of a film to be etched). Accordingly “a film whose etching rate is high” represents a film which is easily etched, and “a film whose etching rate is low” represents a film which is difficult to be etched. In addition, “the etching selectivity between an A layer and a B layer can be obtained” means that when the A layer and the B layer are etched, there is a sufficient difference between the etching rate of the A layer and the etching rate of the B layer, so that a larger amount of one of the A layer and the B layer can be etched than the other, for example.

Note that an example of oxide semiconductors which can be used in this specification includes InMO₃(ZnO)_(m), (m>0). Here, “M” is a metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn) and cobalt (Co). For example, when M includes Ga, only Ga is included, or the above metal element is included in addition to Ga, for example, M includes Ga and Na, Ga and Fe, or the like. Further, in the above oxide semiconductor, a transition metal element such as Fe or Ni, or an oxide of the transition metal may be included as an impurity element in addition to the element included as M. In this specification, among the above oxide semiconductors, an oxide semiconductor including at least gallium as M is referred to as an In—Ga—Zn—O based oxide semiconductor, and a thin film using the material is referred to as an In—Ga—Zn—O based non-single-crystal film in some cases.

Note that a semiconductor device in this specification refers to all devices which function by utilizing semiconductor characteristics. Display devices, semiconductor circuits, and electronic devices are all semiconductor devices.

According to an embodiment of the present invention disclosed, the island-shaped oxide semiconductor layer functioning as an active layer and the conductive layer covering the island-shaped oxide semiconductor layer are processed by dry etching, whereby the semiconductor device can be miniaturized and performance of the semiconductor device is improved. Further the oxide semiconductor layer above the gate insulating layer is processed by wet etching into an island-shaped oxide semiconductor, so that throughput can be improved.

In addition, etching of the oxide semiconductor layer over the gate insulating layer, which does not need control of the etching relatively, is performed by wet etching and channel etching which needs miniaturization and control of etching is performed by dry etching, so that throughput can be improved in the whole manufacturing process and higher performance of the semiconductor device can be achieved.

Further, wet etching is employed when the oxide semiconductor layer is processed so as to have an island shape, and a material such as indium included in the oxide semiconductor layer is collected from a wasted solution after the etching and reused, so that the resources can be effectively used and cost can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, 1C, 1D, and 1E illustrate a semiconductor device according to Embodiment 1.

FIGS. 2A, 2B, 2C, 2D, and 2E illustrate a semiconductor device according to Embodiment 2.

FIGS. 3A, 3B, 3C, 3D, and 3E illustrate a method for manufacturing a semiconductor device according to Embodiment 2.

FIG. 4 is a graph showing the dependence of an etching rate and a selectivity on an oxygen content.

FIGS. 5A, 5B, and 5C illustrate a method for manufacturing a semiconductor device according to Embodiment 3.

FIGS. 6A, 6B, and 6C illustrate a method for manufacturing the semiconductor device according to Embodiment 3.

FIG. 7 illustrates a method for manufacturing the semiconductor device according to Embodiment 3.

FIG. 8 illustrates a method for manufacturing the semiconductor device according to Embodiment 3.

FIG. 9 illustrates a method for manufacturing the semiconductor device according to Embodiment 3.

FIG. 10 illustrates the semiconductor device according to Embodiment 3.

FIGS. 11A1, 11A2, 1161, and 11B2 illustrate the semiconductor device according to Embodiment 3.

FIG. 12 illustrates a semiconductor device according to Embodiment 3.

FIG. 13 illustrates a semiconductor device according to Embodiment 4.

FIGS. 14A and 14B are block diagrams showing semiconductor devices.

FIG. 15 illustrates a bloke diagram showing a structure of a signal line driver circuit.

FIG. 16 is a timing chart showing operation of the signal line driver circuit.

FIG. 17 is a timing chart showing operation of the signal line driver circuit.

FIG. 18 is a diagram showing a structure of a shift register.

FIG. 19 is a diagram showing a connection structure of a flip flop shown in FIG. 18.

FIG. 20 is a diagram showing an equivalent circuit of a pixel of a semiconductor device according to Embodiment 6.

FIGS. 21A, 21B, and 21C illustrate semiconductor devices according to Embodiment 6.

FIGS. 22A1, 22A2, and 22 B illustrate a semiconductor device according to Embodiment 5.

FIG. 23 illustrates a semiconductor device according to Embodiment 6.

FIGS. 24A and 24B illustrate a semiconductor device according to Embodiment 6.

FIGS. 25A and 25B illustrate examples of the usage mode of electronic paper.

FIG. 26 is an external view illustrating an example of an electronic book.

FIG. 27A is an external view of a television device and FIG. 27B is an external view of a digital photo frame.

FIGS. 28A and 28B are external views illustrating examples of game machines.

FIGS. 29A and 29B are external views illustrating examples of mobile phones.

DETAILED DESCRIPTION OF THE INVENTION

As the substrate 200 having an insulating surface, for example, a glass substrate having a visible light transmitting property, which is used for a liquid crystal display device or the like, can be used. The glass substrate is preferably an alkali-free glass substrate. As an alkali-free glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. In addition, as the substrate 200 having an insulating surface, an insulating substrate which is formed of an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate; a semiconductor substrate which is formed of a semiconductor material such as silicon and whose surface is covered with an insulating material; a conductive substrate which is formed of a conductor such as metal or stainless steel and 3whose surface is covered with an insulating material; or the like can also be used.

Embodiment 1

In this embodiment, an example of a method for manufacturing a semiconductor device is described with reference to FIGS. 1A to 1E.

First, a gate electrode 202 is formed over a substrate 200 having an insulating surface and then a gate insulating layer 204 and an oxide semiconductor layer 206 are formed over the gate electrode 202 (see FIG. 1A).

As the substrate 200 having an insulating surface, for example, a glass substrate having a visible light transmitting property, which is used for a liquid crystal display device or the like, can be used. The glass substrate is preferably an alkali-free glass substrate. As an alkali-free glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. In addition, as the substrate 200 having an insulating surface, an insulating substrate which is formed of an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate; a semiconductor substrate which is formed of a semiconductor material such as silicon and whose surface is covered with an insulating material; a conductive substrate which is formed of a conductor such as metal or stainless steel and whose surface is covered with an insulating material; or the like can also be used.

A conductive layer is formed over the entire surface of the substrate 200 and then the conductive layer is selectively etched using a resist mask formed by a photolithography method, so that the gate electrode 202 can be formed. At this time, in order to improve the coverage of the gate electrode 202 with the gate insulating layer 204 formed later and preventing disconnection, the gate electrode 202 is preferably etched so that end portions thereof have a tapered shape. Note that the gate electrode 202 includes an electrode and a wiring, such as a gate wiring, formed using the conductive layer.

The gate electrode 202 is desirably formed using a low resistance conductive material such as aluminum (Al) or copper (Cu). Note that in the case where aluminum is used for the wiring and the electrode, aluminum has disadvantages such as low heat resistance and a tendency to be corroded when aluminum is used by itself; therefore, aluminum is preferably used in combination with a heat-resistant conductive material.

As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including the above element as its component, an alloy film including a combination of these elements, or a nitride including the above element as its component is used. A film formed using such a heat-resistant conductive material and aluminum (or copper) are stacked, so that the wiring and the electrode can be formed.

The gate insulating layer 204 can be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a tantalum oxide film, or the like. Alternatively, the gate insulating layer 204 may be formed using a stack of these films. The film can be formed to a thickness of 50 nm to 250 nm inclusive by a sputtering method or the like. For example, as the gate insulating layer 204, a silicon oxide film can be formed to a thickness of 100 nm by a sputtering method.

Note that before the oxide semiconductor layer 206 is formed over the gate insulating layer 204, a surface of the gate insulating layer 204 may be subjected to plasma treatment. Dust attaching to the surface of the gate insulating layer 204 can be removed by the plasma treatment.

Plasma treatment can be performed in such a manner that an inert gas such as an argon (Ar) gas is introduced into a vacuum chamber, and a bias voltage is applied to a processing object (here, the substrate 200 over which the gate insulating layer 204 is formed) so that a plasma state is generated. In this case, electrons and cations of Ar exist in the plasma and cations of Ar are accelerated in a cathode direction (toward the substrate 200 side). The accelerated cations of Ar collide with the surface of the gate insulating layer 204, whereby the surface of the gate insulating layer 204 is etched by sputtering so as to be reformed. In place of an argon gas, a helium gas may be used. Alternatively, the plasma treatment may be performed in an argon atmosphere to which oxygen, hydrogen, nitrogen, and/or the like is added. Further alternatively, the plasma treatment may be performed in an argon atmosphere to which Cl₂, CF₄, and/or the like is added. Such plasma treatment described above is also referred to as “reverse sputtering” in some cases.

The oxide semiconductor layer 206 can be formed using an In—Ga—Zn—O based non-single-crystal film. For example, the oxide semiconductor layer 206 is formed by a sputtering method using an oxide semiconductor target including In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1). For example, the following conditions may be employed for the sputtering: a distance between the substrate 200 and the target is 30 mm to 500 mm; the pressure is 0.1 Pa to 2.0 Pa; the DC power source is 0.25 kW to 5.0 kW (when the target with a size of 8-inch in diameter is used); and the atmosphere is an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen.

Note that a pulsed DC power source is preferably used because dust can be reduced and thickness can be uniformed. In addition, the above plasma treatment is performed and then the oxide semiconductor layer 206 is formed without being exposed to the air, so that dust or moisture can be prevented from attaching to an interface between the gate insulating layer 204 and the oxide semiconductor layer 206. The thickness of the oxide semiconductor layer 206 may be approximately 5 nm to 200 nm.

As the above sputtering method, an RF sputtering method in which a high frequency power source is used as a sputtering power source, a DC sputtering method, a pulsed DC sputtering method in which direct current bias is applied in pulses, or the like can be employed.

Alternatively, a multi-target sputtering apparatus in which a plurality of targets which are formed of different materials from each other may be used. In a multi-target sputtering apparatus, a stack of different films can be formed in one chamber, or one film can be formed by sputtering using plural kinds of materials at the same time in one chamber. Alternatively, a method using a magnetron sputtering apparatus in which a magnetic field generating system is provided inside the chamber (a magnetron sputtering method), an ECR sputtering method in which plasma generated by using a micro wave is used, or the like may be employed. Further alternatively, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other to form a compound thereof at the time of film formation, a bias sputtering method in which a voltage is applied also to the substrate at the time of film formation, or the like may be employed.

Next, a resist mask 208 is formed over the oxide semiconductor layer 206. Then the oxide semiconductor layer 206 is selectively etched using the resist mask 208, so that an island-shaped oxide semiconductor layer 210 is formed (see FIG. 1B).

Here, the island-shaped oxide semiconductor layer 210 is formed by removing an unnecessary portion of the oxide semiconductor layer 206 by wet etching with the use of ITO07N (manufactured by Kanto Chemical Co., Inc.) or a mixed solution of acetic acid, nitric acid, and phosphoric acid. Note that after the above etching, the resist mask 208 is removed. In addition, an etchant for the wet etching is not limited to the above solution as long as the oxide semiconductor layer 206 can be etched using the etchant.

As the above etching, wet etching is preferably employed. This is because a large area can be processed uniformly in a short time by wet etching. Note that when wet etching is employed, a material such as indium can be collected from a wasted solution obtained after etching and reused. Also in view of effective use of resources, wet etching is preferably employed as the above etching. On the other hand, even when dry etching is employed, the island-shaped oxide semiconductor layer 210 can be formed. Therefore, dry etching should not be excluded from the above etching.

Next, a conductive layer 212 is formed over the island-shaped oxide semiconductor layer 210 (see FIG. 1C).

The conductive layer 212 can be formed by a sputtering method, a vacuum evaporation method, or the like, using a metal including an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy including any of the above elements, nitride including any of the above elements, or the like. Note that in the case where heat treatment (e.g., heat treatment at approximately 200° C. to 600° C.) is performed after formation of the conductive layer 212, the conductive layer 212 preferably has a given heat resistant property.

For example, the conductive layer 212 can be formed with a single-layer structure of a titanium film. Alternatively, the conductive layer 212 is formed with a stacked-layer structure. For example, the conductive layer 212 can be formed with a stacked-layer structure of an aluminum film and a titanium film. Further alternatively, a three-layer structure of a titanium film, an aluminum film including neodymium (Al—Nd), and a titanium film may be employed. Further alternatively, the conductive layer 212 may be formed with a single-layer structure of an aluminum film including silicon.

Next, resist masks 214 a, 214 b, and 214 c are formed over the conductive layer 212. Then, the conductive layer 212 is selectively etched so that conductive layers 216 a, 216 b, and 218 are formed, and part of the island-shaped oxide semiconductor layer 210 (a part near a surface thereof) is removed (channel-etched), so that a recessed portion 220 is formed in the island-shaped oxide semiconductor layer 210 (see FIG. 1D).

The recessed portion 220 formed by removing the part of the island-shaped oxide semiconductor layer 210 corresponds a region between the conductive layer 216 a and the conductive layer 216 b. Therefore, the conductive layer 216 a functions as one of a source electrode and a drain electrode of the transistor, and the conductive layer 216 b functions as the other of the source electrode and the drain electrode. As illustrated in FIG. 1D, the recessed portion 220 is formed by removing the part of the oxide semiconductor layer 210, whereby the conductive layer 216 a and the conductive layer 216 b are electrically insulated from each other without fault. In addition, the conductive layer 218 functions as a wiring electrically connects elements such as the transistor.

Note that after the above etching, the resist masks 214 a, 214 b, and 214 c are removed.

As the etching at this time, dry etching is preferably employed. By employing dry etching, a wiring structure or the like can be miniaturized as compared to the case of using wet etching. In addition, because controllability of etching is high by employing dry etching, removal of the part of the island-shaped oxide semiconductor layer 210 (formation of the recessed portion 220) can be performed with high controllability.

As the above dry etching, in particular, dry etching using a gas including chlorine is preferably employed. By etching using a gas including a chlorine, variation of etching in the surface can be reduced as compared to the case of using a gas without chlorine.

The above gas including chlorine is more preferable when oxygen is added thereto. This is because, by using a gas including chlorine and oxygen, etching selectivity between the gate insulating layer 204 and the island-shaped oxide semiconductor layer 210 are easily obtained and damage to the gate insulating layer 204 can be reduced sufficiently. Note that in this case, a material including silicon oxide, such as silicon oxide, a silicon oxynitride, or silicon nitride oxide is preferably used as the gate insulating layer 204. In addition, when an oxygen gas content in the etching gas is set to 15 volume % or more, etching selectivity between the island-shaped oxide semiconductor layer 210 and the gate insulating layer 204 becomes large, so that damage to the gate insulating layer 204 can be effectively reduced.

As the gas used for the dry etching, a chlorine-based gas such as boron chloride (BCl₃), silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄); a fluorine-based gas such as carbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride (NF₃), or trifluoromethane (CHF₃); hydrogen bromide (HBr); oxygen (O₂); any of these gases to which a rare gas such as helium (He), or argon (Ar) is added; or the like can be used as well as chlorine (Cl₂).

In addition, as a material for the conductive layer 212, a material whose etching rate is higher than that of the island-shaped oxide semiconductor layer 210 is preferably used. This is because when the conductive layer 212 and the island-shaped oxide semiconductor layer 210 are etched at one time by dry etching, the etching rate of the island-shaped oxide semiconductor layer 210 is made smaller than that of the conductive layer 212, so that the island-shaped oxide semiconductor layer 210 can be prevented from being etched excessively. As a result, elimination of the oxide semiconductor layer 210 can be prevented.

After that, heat treatment is preferably performed at 200° C. to 600° C., typically 300° C. to 500° C. Here, heat treatment is performed at 350° C. under a nitrogen atmosphere for 1 hour. By this heat treatment, rearrangement at an atomic level of the In—Ga—Zn—O based oxide semiconductor included in the island-shaped oxide semiconductor layer 210 is performed. This heat treatment (including photo annealing and the like) is important because this heat treatment enables release of distortion which interrupts transfer of carriers in the island-shaped oxide semiconductor layer 210. Note that there is no particular limitation on timing of the above heat treatment as long as the heat treatment is performed after formation of the oxide semiconductor layer 206.

In addition, the recessed portion 220 of the exposed part of the island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By performing the oxygen radical treatment, the thin film transistor in which the island-shaped oxide semiconductor layer 210 is a channel formation region can be normally off. Further, by performing radical treatment, damage to the island-shaped oxide semiconductor layer 210 due to etching can be repaired. The radical treatment is preferably performed under an O₂ atmosphere; an N₂O atmosphere; an N₂, He, or Ar atmosphere including oxygen; or the like. In addition, radical treatment may be performed under an atmosphere which is the above atmosphere to which Cl₂ and/or CF₄ is added. Note that radical treatment is preferably performed without application of a bias voltage on the substrate 100 side.

Next, a protective insulating layer 222 is formed so as to cover the thin film transistor 250 including the gate electrode 202, the island-shaped oxide semiconductor layer 210, the conductive layer 216 a, the conductive layer 216 b, and the like (see FIG. 1E). The protective insulating layer 222 may be formed by a sputtering method or the like using a material including silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxide, tantalum oxide, or the like.

After that, various kinds of electrodes and wirings are formed, so that the semiconductor device is completed.

As described above, in this embodiment, the island-shaped oxide semiconductor layer functioning as an active layer and the conductive layer covering the island-shaped oxide semiconductor layer are processed by dry etching, whereby the semiconductor device can be miniaturized and performance of the semiconductor device can be improved. Alternatively, the oxide semiconductor layer over the gate insulating layer is processed by wet etching into the island-shaped oxide semiconductor layer, so that throughput can be improved. In other words, etching of the oxide semiconductor layer over the gate insulating layer (processing for forming the island-shaped oxide semiconductor layer), which does not need controllability of the etching relatively, is performed by wet etching and channel etching, which needs miniaturization and controllability of etching is performed by dry etching, so that throughput of the whole manufacturing process can be improved and high performance of the semiconductor device can be achieved. In addition, wet etching is employed when the oxide semiconductor layer is processed so as to have an island shape, and a material such as indium included in the oxide semiconductor layer is collected from a wasted solution after the etching and reused, so that the resources can be effectively used and cost can be reduced.

According to this embodiment, a semiconductor device having high characteristics can be provided at low cost. Note that this embodiment can be implemented in combination with any of the other embodiments as appropriate.

Embodiment 2

In this embodiment, a method for manufacturing a semiconductor device, which is different from that of the above embodiment, is described with reference to drawings. Note that many steps of the method for manufacturing a semiconductor device in this embodiment are common to those of Embodiment 1. Therefore, repeated description of the common steps is omitted and description of steps different from that of Embodiment 1 is made below.

First, a gate electrode 202 is formed over a substrate 200 having an insulating surface and then a gate insulating layer 204 is formed over the gate electrode 202. After that, an oxide semiconductor layer 206 and an oxide semiconductor layer 207 are stacked thereover (see FIG. 2A).

The materials and manufacturing method of the gate electrode 202, the gate insulating layer 204, and the oxide semiconductor layer 206 can be referred to Embodiment 1.

The oxide semiconductor layer 207 can be formed using an In—Ga—Zn—O based non-single-crystal film. For example, the oxide semiconductor layer 207 can be formed over the oxide semiconductor layer 206 by a sputtering method using an oxide semiconductor target including In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1). At this time, it is preferable that the oxide semiconductor layer 207 is successively formed so that the oxide semiconductor layer 206 is not exposed to the air.

Note that the oxide semiconductor layer 207 can be formed using the target (In₂O₃:Ga₂O₃:ZnO=1:1:1) used for formation of the oxide semiconductor layer 206. As for sputtering conditions, for example, the temperature can be 20° C. to 100° C., the pressure can be 0.1 Pa to 2.0 Pa, the power is 250 W to 3 kW (in the case of 8-inch φ). In addition, an argon gas is introduced at a flow rate of 40 sccm. By controlling a ratio of components of the target or other sputtering formation conditions as appropriate, the presence or absence, density, and the like of a crystal grain can be controlled. The diameter of the crystal grain can be 1 nm to 10 nm approximately. The thickness of the oxide semiconductor layer 207 may be 2 nm to 20 nm approximately. Needless to say, when the crystal grain is included in the film, the size of the crystal grain does not exceed the thickness of the film.

Here, it is preferable that the formation conditions of the oxide semiconductor layer 206 are different from those of the oxide semiconductor layer 207. For example, the flow rate ratio of an oxygen gas to an argon gas in the formation conditions of the oxide semiconductor layer 206 is larger than the flow rate ratio of an oxygen gas to an argon gas in the formation conditions of the oxide semiconductor layer 207. Specifically, for the formation condition of the oxide semiconductor layer 207, a rare gas (argon, helium, or the like) atmosphere, or an atmosphere including an oxygen gas at 10% or less and a rare gas at 90% or more is employed. For the formation conditions of the oxide semiconductor layer 206, an oxygen atmosphere or an atmosphere in which the flow rate ratio of an oxygen gas to a rare gas is 1 or more is employed.

Note that the oxide semiconductor layer 206 and the oxide semiconductor layer 207 may be formed using different materials.

Next, a resist mask 208 is formed over the oxide semiconductor layer 207, and the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are selectively etched using the resist mask 208, so that an island-shaped oxide semiconductor layer 210 and an island-shaped oxide semiconductor layer 211 are formed (see FIG. 2B).

Here, the island-shaped oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 are formed by removing unnecessary portions of the oxide semiconductor layer 206 and the oxide semiconductor layer 207 by wet etching with the use of ITO07N (manufactured by Kanto Chemical Co., Inc.) or a mixed solution of acetic acid, nitric acid, and phosphoric acid. Note that after the above etching, the resist mask 208 is removed. In addition, an etchant for wet etching is not limited to the above solutions as long as the oxide semiconductor layer 206 and the oxide semiconductor layer 207 can be etched using the etchant.

As the above etching, wet etching is preferably employed. This is because a large area can be processed uniformly in a short time by wet etching. Note that when wet etching is employed, a material such as indium can be collected from a wasted solution obtained after etching and reused. Also in view of effective use of resources, wet etching is preferably employed as the above etching. On the other hand, even when dry etching is employed, the island-shaped oxide semiconductor layer 210 and the island oxide semiconductor layer 211 can be formed. Therefore, dry etching should not be excluded from the above etching.

Next, a conductive layer 212 is formed over the island-shaped oxide semiconductor layer 211 (see FIG. 2C). The material and manufacturing method of the conductive layer 212 can be referred to Embodiment 1.

Next, resist masks 214 a, 214 b, and 214 c are formed over the conductive layer 212. Then, the conductive layer 212 is selectively etched, so that conductive layers 216 a, 216 b, and 218 are formed, and at the same time, the island-shaped oxide semiconductor layer 211 is etched to form semiconductor regions 215 a and 215 b whose conductivity is high, and part of the island-shaped oxide semiconductor layer 210 (the part near a surface thereof) is removed (channel-etched) (see FIG. 2D).

A recessed portion 220 formed by removing the part of the island-shaped oxide semiconductor layer 210 corresponds to a region which is between the conductive layer 216 a and the conductive layer 216 b and also between the semiconductor region 215 a whose conductivity is high and the semiconductor region 215 b whose conductivity is high. Therefore, the conductive layer 216 a functions as one of a source electrode and a drain electrode of the transistor, while the conductive layer 216 b functions as the other of the source electrode and the drain electrode.

Note that after the above etching, the resist masks 214 a, 214 b, and 214 c are removed.

As the etching at this time, dry etching is preferably employed. By employing dry etching, a wiring structure or the like can be miniaturized as compared to the case of using wet etching. In addition, because controllability of etching is high by employing dry etching, removal of the part of the island-shaped oxide semiconductor layer 210 (formation of the recessed portion 220) can be performed with high controllability.

As the above dry etching, in particular, dry etching using a gas including chlorine is preferably employed. By etching using a gas including a chlorine, variation of etching in the surface can be reduced as compared to the case of using a gas without chlorine.

The above gas including chlorine is more preferably when oxygen is added thereto. This is because, by using a gas including chlorine and oxygen, etching selectivity between the gate insulating layer 204 and the island-shaped oxide semiconductor layer 210 (also the island-shaped oxide semiconductor layer 211) are easily obtained and damage to the gate insulating layer 204 can be reduced sufficiently. Note that in this case, a material including silicon oxide, such as silicon oxide, a silicon oxynitride, or silicon nitride oxide is preferably used as the gate insulating layer 204. In addition, when an oxygen gas content in the etching gas is set to 15 volume % or more, etching selectivity of the island-shaped oxide semiconductor layer 210 to the gate insulating layer 204 becomes large, so that damage to the gate insulating layer 204 can be effectively reduced.

As the gas used for dry etching, a chlorine-based gas such as boron chloride (BCl₃), silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄); a fluorine-based gas such as carbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride (NF₃), or trifluoromethane (CHF₃); hydrogen bromide (HBr); oxygen (O₂); any of these gases to which a rare gas such as helium (He), argon (Ar) is added; or the like can be used as well as chlorine (Cl₂).

In addition, as a material for the conductive layer 212, a material whose etching rate is higher than those of the island-shaped oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 is preferably used. This is because when the conductive layer 212, the island-shaped oxide semiconductor layer 210, and the island-shaped oxide semiconductor layer 211 are etched at one time by dry etching, the etching rate of the island-shaped oxide semiconductor layer 210 and the etching rate of the island-shaped oxide semiconductor layer 211 are set to be smaller than that of the conductive layer 212, so that the island-shaped oxide semiconductor layer 210 can be prevented from being etched excessively. In particular, when the island-shaped oxide semiconductor layer 211 whose etching rate is smaller than that of the conductive layer 212 is provided, the island-shaped oxide semiconductor layer 210 can be effectively prevented from being etched excessively.

It is preferable that the etching rate of the island-shaped oxide semiconductor layer 211 is higher than that of the island-shaped oxide semiconductor layer 210 because separation between the semiconductor region 215 a whose conductivity is high and the semiconductor region 215 b whose conductivity is high, and removal of the part of the island-shaped oxide semiconductor layer 210 can be favorably performed.

After that, heat treatment is preferably performed at 200° C. to 600° C., typically 300° C. to 500° C. In addition, the recessed portion 220 of the exposed part of the island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. The detail thereof can be referred to Embodiment 1.

Next, a protective insulating layer 222 is formed so as to cover the thin film transistor 250 including the gate electrode 202, the island-shaped oxide semiconductor layer 210, the island-shaped oxide semiconductor layer 211, the conductive layer 216 a, and the conductive layer 216 b, and the like (see FIG. 2E). The protective insulating layer 222 may be formed by a sputtering method or the like using a material including silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxide, tantalum oxide, or the like.

After that, various kinds of electrodes and wirings are formed, so that the semiconductor device is completed.

As described above, in this embodiment, the island-shaped oxide semiconductor layer functioning as an active layer and the conductive layer covering the island-shaped oxide semiconductor layer are processed by dry etching, whereby the semiconductor device can be miniaturized and performance of the semiconductor device is improved. Alternatively, the oxide semiconductor layer above the gate insulating layer is processed by wet etching into an island-shaped oxide semiconductor layer, so that throughput can be improved. In other words, etching of the oxide semiconductor layer above the gate insulating layer (processing for forming the island-shaped oxide semiconductor layer), which does not need controllability of etching relatively, is performed by wet etching and channel etching, which needs miniaturization and controllability of etching, is performed by dry etching, so that throughput can be improved in the whole manufacturing process and high performance of the semiconductor device can be achieved. In addition, wet etching is employed when the oxide semiconductor layer is processed so as to have an island shape, and a material such as indium included in the oxide semiconductor layer is collected from a wasted solution after the etching and reused, so that the resources can be effectively used and cost can be reduced.

In addition, in this embodiment, the semiconductor region 215 a whose conductivity is high is formed between the island-shaped oxide semiconductor layer 210 and the conductive layer 216 a, and the semiconductor region 215 b whose conductivity is high is formed between the island-shaped oxide semiconductor layer 210 and the conductive layer 216 b.

Note that this embodiment describes the case where the oxide semiconductor layer 207 is formed over the oxide semiconductor layer 206 and then the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are processed at one time; however, this embodiment is not limited to this manufacturing order. For example, the following process may be employed: the oxide semiconductor layer 206 is formed (see FIG. 3A) and then processed to be the island-shaped oxide semiconductor layer 210 (see FIG. 3B); then, the oxide semiconductor layer 207 and the conductive layer 212 are formed so as to cover the island-shaped oxide semiconductor layer 210 (see FIG. 3C); and the oxide semiconductor layer 207 and the conductive layer 212 are processed at one time (see FIGS. 3D and 3E). In this case, damage to part to be exposed of the gate insulating layer 204 can be reduced at the time of etching the conductive layer 212. In particular, when the oxide semiconductor layer 207 whose etching rate is smaller than that of the conductive layer 212 is provided, damage to the part to be exposed of the gate insulating layer 204 can be effectively reduced.

According to this embodiment, a semiconductor device having high characteristics can be provided at low cost. Note that this embodiment can be implemented in combination with any of the other embodiments as appropriate.

Embodiment 3

In this embodiment, a method for manufacturing a display device which is an example of a usage mode of a semiconductor device is described with reference to drawings. Note that many steps of the manufacturing method described in this embodiment are common to those of Embodiment 1 or Embodiment 2. Therefore, repeated description of the common steps is omitted and description of steps different from that of Embodiment 1 or Embodiment 2 is made below. Note that in the description below, FIGS. 5A to 5C and FIGS. 6A to 6C are cross-sectional views and FIG. 7, FIG. 8, FIG. 9, and FIG. 10 are top views.

First, wirings and an electrode (a gate wiring including a gate electrode 202, a capacitor wiring 108, and a first terminal 121) are formed over a substrate 200 having an insulating surface (see FIG. 5A and FIG. 7).

The capacitor wiring 108 and the first terminal 121 can be formed at the same time and using the same material as the gate electrode 202. Note that the material and manufacturing method of the gate electrode 202 can be referred to Embodiment 1.

Next, an island-shaped oxide semiconductor layer 210 and an island-shape oxide semiconductor layer 211 are formed over the gate electrode 202 with a gate insulating layer 204 interposed therebetween (see FIG. 5B and FIG. 8). The materials and manufacturing methods of the island-shaped oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 can be referred to Embodiments 1 and 2.

Next, a contact hole 213 is formed in the gate insulating layer 204 so that the first terminal 121 is exposed. After that, a conductive layer 212 is formed so as to cover the gate insulating layer 204, the island-shaped oxide semiconductor layer 210, and the island-shaped oxide semiconductor layer 211 (see FIG. 5C).

The material and manufacturing method of the conductive layer 212 can be referred to Embodiment 1. Note that in this embodiment, the conductive layer 212 and the first terminal 121 are electrically connected to each other through the contact hole 213.

Next, a resist mask 214 is formed over the conductive layer 212. Then, the conductive layer 212 is selectively etched to form conductive layers 216 a and 216 b, a connection electrode 120, and a second terminal 122. At the same time, the oxide semiconductor layer 211 is etched to form a semiconductor region 215 a whose conductivity is high and a semiconductor region 215 b whose conductivity is high, and a part of the oxide semiconductor layer 210 (the part near the surface thereof) is removed to form a recessed portion 220 in the oxide semiconductor layer 210 (see FIG. 6A and FIG. 9).

The second terminal 122 can be formed so as to be electrically connected to a source wiring (the source wiring including the conductive layer 216 a or the conductive layer 216 b). In addition, the connection electrode 120 can be formed so as to be directly connected to the first terminal 121 through the contact hole 213 formed in the gate insulating layer 204.

As the etching at this time, dry etching is preferably employed. By employing dry etching, a wiring structure or the like can be miniaturized as compared to the case of using wet etching. In addition, because controllability of etching is high by employing dry etching, removal of the part of the island-shaped oxide semiconductor layer 210 (formation of the recessed portion 220) can be performed with high controllability. Note that a gas used for dry etching and the like can be referred to Embodiments described above.

Next, heat treatment is preferably performed at 200° C. to 600° C., typically 300° C. to 500° C. For example, heat treatment is performed at 350° C. under a nitrogen atmosphere for 1 hour. By this heat treatment, rearrangement at an atomic level of the In—Ga—Zn—O based non-single-crystal film included in the island-shaped oxide semiconductor layer 210 is performed. This heat treatment (including photo annealing) is effective because this heat treatment enables release of distortion which interrupts transfer of carriers. Note that there is no particular limitation on timing of the heat treatment as long as the heat treatment is performed after formation of the oxide semiconductor layer 211. For example, the heat treatment may be performed after formation of a pixel electrode.

In addition, the exposed part of the island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By performing the oxygen radical treatment, the thin film transistor in which the island-shaped oxide semiconductor layer 210 is a channel formation region can be normally off. Further, by performing radical treatment, damage to the island-shaped oxide semiconductor layer 210 due to etching can be repaired. The radical treatment is preferably performed under an O₂ or N₂O atmosphere, or preferably, an N₂, He, or Ar atmosphere including oxygen. In addition, radical treatment may be performed under an atmosphere which is the above atmosphere to which Cl₂ and/or CF₄ is added.

Next, the resist mask 214 is removed, and then, a protective insulating layer 222 is formed to cover a thin film transistor 250. The protective insulating layer 222 is selectively etched, so that a contact hole 125 reaching the conductive layer 216 b, a contact hole 126 reaching the connection electrode 120, and a contact hole 127 reaching the second terminal 122 are formed (see FIG. 6B).

After that, a transparent conductive layer 110 electrically connected to the conductive layer 216, a transparent conductive layer 128 electrically connected to the connection electrode 120, and a transparent conductive layer 129 electrically connected to the second terminal 122 are formed (see FIG. 6C and FIG. 10).

The transparent conductive layer 110 functions as a pixel electrode. The transparent conductive layers 128 and 129 serve as electrodes or wirings which are used for connection to an FPC. In particular, the transparent conductive layer 128 formed over the connection electrode 120 can be used as a connection terminal electrode which functions as an input terminal for the gate wiring. The transparent conductive layer 129 formed over the second terminal 122 can be used as a connection terminal electrode which functions as an input terminal for the source wiring.

In addition, the capacitor wiring 108, the gate insulating layer 204, the protective insulating layer 222, and the transparent conductive layer 110 can form a storage capacitor. In this case, the capacitor wiring 108 and the transparent conductive layer 110 serve as electrodes, and the gate insulating layer 204 and the protective insulating layer 222 serve as dielectrics.

The transparent conductive layers 110, 128, and 129 can be formed by a sputtering method, a vacuum evaporation method, or the like, using indium oxide (In₂O₃), an alloy of indium oxide and tin oxide (In₂O₃—SnO₂, hereinafter, abbreviated as ITO), an alloy of indium oxide and zinc oxide (In₂O₃—ZnO), or the like. For example, a transparent conductive film is formed and then a resist mask is formed over the transparent conductive film. Then, unnecessary portions are removed by etching, so that the transparent conductive layers 110, 128, and 129 can be formed.

FIGS. 11A1 and 11A2 are a cross-sectional view and a top view of a terminal portion of the gate wiring, respectively. FIG. 11A1 corresponds to the cross-sectional view taken along line C1-C2 in FIG. 11A2. In FIG. 11A1, the transparent conductive layer 128 formed over the protective insulating layer 222 is a connection terminal electrode which functions as an input terminal. In addition, in FIG. 11A1, the first terminal 121 whose material is the same as the material of the gate wiring, and the connection electrode 120 whose material is the same as the material of the source wiring are overlapped with each other with the gate insulating layer 204 interposed therebetween and directly in contact with each other at the terminal portion to be brought into conduction. In addition, the connection electrode 120 and the transparent conductive layer 128 are directly in contact with each other through the contact hole formed in the protective insulating layer 222 and brought into conduction.

FIGS. 11B1 and 11B2 are a cross-sectional view and a top view of a terminal portion of the source wiring at this time, respectively. FIG. 11B1 corresponds to the cross sectional view taken along line D1-D2 in FIG. 11B2. In FIG. 11B1, the transparent conductive layer 129 formed over the protective insulating layer 222 is a connection terminal electrode which functions as an input terminal. In addition, FIG. 11B1 illustrates the case where an electrode 156 whose material is the same as the material of the gate wiring is positioned below the second terminal 122 which is electrically connected to the source wiring and overlaps with the second terminal 122 at the terminal portion with the gate insulating layer 204 interposed therebetween. The electrode 156 is not electrically connected to the second terminal 122. If the electrode 156 is set to a potential different from the potential of the second terminal 122, for example, floating, GND, 0 V, or the like, a capacitor which is useful against noise or static electricity can be formed. In addition, the second terminal 122 is electrically connected to the transparent conductive layer 129 with the protective insulating layer 222 interposed therebetween.

In accordance with the density of pixels, a plurality of the gate wirings, the source wirings, and the capacitor wirings are provided. Further, a plurality of terminals including the first terminal having the same potential as the gate wiring, the second terminal having the same potential as the source wiring, a third terminal having the same potential as the capacitor wiring, and the like are arranged at the terminal portion. The respective numbers of the terminals can be given numbers set by practitioners appropriately.

Through the above process, elements such as an n-channel bottom-gate thin film transistor and a storage capacitor can be completed with the use of six photomasks. In addition, these elements are arranged in matrix so as to correspond to respective pixels, whereby one substrate used for manufacturing an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate, for convenience.

In order to manufacturing an active matrix liquid crystal display device, a liquid crystal layer is formed between an active matrix substrate and a counter substrate provided with a counter electrode, and then, the active matrix substrate and the counter substrate are fixed. Note that a common electrode which is electrically connected to the counter electrode provided for the counter substrate is formed over the active matrix substrate. A fourth terminal which is electrically connected to the common electrode is formed at the terminal portion. This fourth terminal serves as a terminal for setting the common electrode to have a fixed potential, for example, GND or 0 V.

The structure according to this embodiment is not limited to the pixel structure in FIG. 10. Another example of the structure is illustrated in FIG. 12. FIG. 12 illustrates the structure in which the pixel electrode and a gate wiring of the adjacent pixel serve as electrodes, and the protective insulating layer and the gate insulating layer serve as dielectrics so that the storage capacitor is formed without the capacitor wiring. In this case, the capacitor wiring and the third terminal which is connected to the capacitor wiring can be omitted.

Note that this embodiment can be implemented in combination with any of the other embodiment as appropriate.

Embodiment 4

In this embodiment, an example in which at least part of a driver circuit and a thin film transistor to be disposed in a pixel portion are formed over one substrate in a display device will be described.

The thin film transistor to be disposed in the pixel portion is formed according to Embodiment 3. Further, the thin film transistor described in Embodiment 3 is an n-channel TFT. Thus, part of a driver circuit that can be formed using n-channel TFTs among driver circuits is formed over the same substrate as the thin film transistor of the pixel portion.

FIG. 14A illustrates an example of a block diagram of an active matrix liquid crystal display device, which is an example of a display device. The display device illustrated in FIG. 14A includes, over a substrate 5300, a pixel portion 5301 including a plurality of pixels each provided with a display element; a scanning line driver circuit 5302 that selects a pixel; and a signal line driver circuit 5303 that controls a video signal input to the selected pixel.

In addition, the thin film transistor described in Embodiment 3 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference to FIG. 15.

The signal line driver circuit illustrated in FIG. 15 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603 a, a second thin film transistor 5603 b, and a third thin film transistor 5603 c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613, and the switch groups 5602_1 to 5602_M are connected to the wirings 5621_1 to 5621_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to three signal lines (a signal line Sm−2, a signal line Sm−1, and a signal line Sm (m=3M)) via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. For example, a wiring 5621_J of the J-th column (any one of the wirings 5621_1 to 5621_M) is connected to a signal line Sj−2, a signal line Sj−1, and a signal line Sj (j=3J) via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c which are included in the switch group 5602_J.

A signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed using a single crystal semiconductor. The switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are preferably connected through an FPC or the like. Alternatively, the driver IC 5601 may be formed using a single crystal semiconductor formed over the same substrate as the pixel portion by a method such as bonding.

Next, operation of the signal line driver circuit illustrated in FIG. 15 is described with reference to a timing chart in FIG. 16. The timing chart in FIG. 16 shows the case where a scanning line Gi of the i-th stage is selected. A selection period of the scanning line Gi of the i-th stage is divided into a first sub-selection period Ti, a second sub-selection period T2, and a third sub-selection period T3. In addition, the signal line driver circuit in FIG. 15 operates as shown in FIG. 16 even when a scanning line of another stage is selected.

Note that the timing chart in FIG. 16 shows the case where the wiring 5621_J in the J-th column is connected to the signal line Sj−2, the signal line Sj−1, and the signal line Sj via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c, respectively.

The timing chart in FIG. 16 shows timing at which the scanning line Gi of the i-th stage is selected, timing 5703 a of on/off of the first thin film transistor 5603 a, timing 5703 b of on/off of the second thin film transistor 5603 b, timing 5703 c of on/off of the third thin film transistor 5603 c, and a signal 5721_J input to the wiring 5621_J of the J-th column.

In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wirings 5621_1 to 5621_M. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj−2, a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj−1, and a video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj. In addition, in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_J are denoted by Data_j−2, Data_j−1, and Data_j, respectively.

As shown in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 input to the wiring 5621_J is input to the signal line Sj−2 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 15, by dividing one gate selection period into three, video signals can be input to three signal lines from one wiring 5621 in one gate selection period. Therefore, in the signal line driver circuit in FIG. 15, the number of connections of the substrate provided with the driver IC 5601 and the substrate provided with the pixel portion can be approximately ⅓ of the number of signal lines. The number of connections is reduced to approximately ⅓ of the number of the signal lines, so that reliability, yield, etc., of the signal line driver circuit in FIG. 15 can be improved.

Note that there are no particular limitations on the arrangement, the number, a driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in the respective sub-selection periods as illustrated in FIG. 15.

For example, when a video signal is input to each of three or more signal lines from one wiring in each of three or more sub-selection periods, it is only necessary to add a thin film transistor and a wiring for controlling the thin film transistor. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, one selection period may be divided into a precharge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 as illustrated in a timing chart in FIG. 17. The timing chart in FIG. 17 illustrates timing at which the scanning line Gi of the i-th stage is selected, timing 5803 a of on/off of the first thin film transistor 5603 a, timing 5803 b of on/off of the second thin film transistor 5603 b, timing 5803 c of on/off of the third thin film transistor 5603 c, and a signal 5821_J input to the wiring 5621_J of the J-th column. As illustrated in FIG. 17, the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c are tuned on in the precharge period Tp. At this time, precharge voltage Vp input to the wiring 5621_J is input to the signal line Sj−2, the signal line Sj−1, and the signal line Sj via the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c, respectively. In the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603 b and the third thin film transistor 5603 c are turned off. At this time, Data_j−2 input to the wiring 5621_J is input to the signal line Sj−2 via the first thin film transistor 5603 a. In the second sub-selection period T2, the second thin film transistor 5603 b is turned on, and the first thin film transistor 5603 a and the third thin film transistor 5603 c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin film transistor 5603 b. In the third sub-selection period T3, the third thin film transistor 5603 c is turned on, and the first thin film transistor 5603 a and the second thin film transistor 5603 b are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin film transistor 5603 c.

As described above, in the signal line driver circuit in FIG. 15 to which the timing chart in FIG. 17 is applied, the video signal can be written to the pixel at high speed because the signal line can be precharged by providing a precharge selection period before a sub-selection period. Note that portions in FIG. 17 which are similar to those of FIG. 16 are denoted by common reference numerals and detailed description of the portions which are the same and portions which have similar functions is omitted.

Further, a structure of a scanning line driver circuit is described. The scanning line driver circuit includes a shift register and a buffer. In addition, the scanning line driver circuit may include a level shifter in some cases. In the scanning line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is produced. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scanning line. Gate electrodes of transistors in pixels of one line are connected to the scanning line. Further, since the transistors in the pixels of one line have to be turned on at the same time, a buffer which can feed a large current is used.

One mode of a shift register which is used for part of a scanning line driver circuit is described with reference to FIG. 18 and FIG. 19.

FIG. 18 illustrates a circuit structure of the shift register. The shift register illustrated in FIG. 18 includes a plurality of flip-flops which are flip-flops 5701_1 to 5701_n. In addition, the shift register is operated with input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

The connection relation of the shift register illustrated in FIG. 18 is described. The flip-flop 5701_1 of a first stage is connected to a first wiring 5711, a second wiring 5712, a fourth wiring 5714, a fifth wiring 5717, a seventh wiring 5717_1, and a seventh wiring 5717_2. The flip-flop 5717_2 of a second stage is connected to a third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 57172, and a seventh wiring 5717_3.

In a similar manner, the flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) of an i-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717_i−1, a seventh wiring 5717_i, and a seventh wiring 5717_i+1. Here, when the “i” is an odd number, the flip-flop 5701_i of the i-th stage is connected to the second wiring 5712; when the “i” is an even number, the flip-flop 5701_i of the i-th stage is connected to the third wiring 5713.

The flip-flop 5701_n of an n-th stage is connected to one of the second wiring 5712 and the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, a seventh wiring 5717_n−1, the seventh wiring 5717_n, and a sixth wiring 5716.

Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power source line and a second power source line, respectively.

Next, FIG. 19 illustrates details of the flip-flop illustrated in FIG. 18. A flip-flop illustrated in FIG. 19 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Each of the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 is an n-channel transistor and is turned on when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

In addition, the flip-flop illustrated in FIG. 19 includes a first wiring 5501, a second wiring 5502, a third wiring 5503, a fourth wiring 5504, a fifth wiring 5505, and a sixth wiring 5506.

Note that all thin film transistors here are enhancement-mode n-channel transistors; however, the present invention is not limited thereto. For example, the driver circuit can be operated using depression-mode n-channel transistors.

Next, a connection structure of the flip-flop illustrated in FIG. 18 is described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506 and a second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

A first electrode and a gate electrode of the third thin film transistor 5573 are connected to the fifth wiring 5505 and a second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, a gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5571, and a second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, a gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501, and a second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571.

A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, a gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572, and a second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571.

A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, a gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502, and a second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571.

A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506, a gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501, and a second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572.

Note that a point at which the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are connected is referred to as a node 5543. A point at which the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are connected is referred to as a node 5544.

Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring 5505 and the sixth wiring 5506 may be referred to as a first power source line and a second power source line, respectively.

In the flip flop 5701_i of the i-th stage, the first wiring 5501 in FIG. 19 is connected to the seventh wiring 5717_i−1 in FIG. 18. The second wiring 5502 in FIG. 19 is connected to the seventh wiring 5717_i+1 in FIG. 18. The third wiring 5503 in FIG. 19 is connected to the seventh wiring 5717_i. The sixth wiring 5506 in FIG. 19 is connected to the fifth wiring 5715.

If the “i” is an odd number, the fourth wiring 5504 in FIG. 19 is connected to the second wiring 5712 in FIG. 18; if the “i” is an even number, the fourth wiring 5504 in FIG. 19 is connected to the third wiring 5713 in FIG. 18. In addition, the fifth wiring 5505 in FIG. 19 is connected to the fourth wiring 5714 in FIG. 18.

Note that in the flip flop 5701_1 of the first stage, the first wiring 5501 in FIG. 19 is connected to the first wiring 5711 in FIG. 18. In addition, in the flip flop 5701_n of the n-th stage, the second wiring 5502 in FIG. 19 is connected to the sixth wiring 5716 in FIG. 18.

Note that the signal line driver circuit and the scanning line driver circuit can be formed using only the n-channel TFTs described in Embodiment 3. The n-channel TFT described in Embodiment 3 has high mobility, and thus a driving frequency of a driver circuit can be increased. In addition, in the n-channel TFT illustrated in Embodiment 3, since parasitic capacitance is reduced by the source and the drain region formed using an In—Ga—Zn—O based non-single-crystal film, the frequency characteristics (referred to as f characteristics) are high. For example, a scanning line driver circuit using the n-channel TFT described in Embodiment 3 can operate at high speed, and thus a frame frequency can be increased and insertion of black images and the like can be realized.

In addition, when the channel width of the transistor in the scanning line driver circuit is increased or a plurality of scanning line driver circuits are provided, a higher frame frequency can be realized. When a plurality of scanning line driver circuits are provided, a scanning line driver circuit for driving even-numbered scanning lines is provided on one side and a scanning line driver circuit for driving odd-numbered scanning lines is provided on the opposite side; thus, increase in frame frequency can be realized. In addition, output of a signal to one scanning line by a plurality of scanning line driver circuits has an advantage of upsizing of the display device.

Further, when an active matrix light-emitting display device, which is an example of a display device, is manufactured, a plurality of transistors are arranged in at least one pixel, and thus a plurality of scanning line driver circuits are preferably arranged. FIG. 14B is a block diagram illustrating an example of an active matrix light-emitting display device.

The light-emitting display device illustrated in FIG. 14B includes, over a substrate 5400, a pixel portion 5401 having a plurality of pixels each provided with a display element, a first scanning line driver circuit 5402 and a second scanning line driver circuit 5404 that select a pixel, and a signal line driver circuit 5403 that controls input of a video signal to the selected pixel.

When the video signal input to a pixel of the display device illustrated in FIG. 14B is a digital signal, a pixel is in a light-emitting state or a non-light-emitting state by switching of on/off of a transistor. Thus, grayscale can be displayed using an area ratio grayscale method or a time ratio grayscale method. An area ratio grayscale method refers to a driving method by which one pixel is divided into a plurality of sub-pixels and each sub-pixel is driven independently based on a video signal so that grayscale is displayed. Further, a time ratio grayscale method refers to a driving method by which a period during which a pixel is in a light-emitting state is controlled so that grayscale is displayed.

Since the response speed of light-emitting elements is higher than that of liquid crystal elements or the like, the light-emitting elements are more suitable for a time ratio grayscale method than liquid-crystal elements. In the case of displaying with a time gray scale method, one frame period is divided into a plurality of sub-frame periods. Then, in accordance with video signals, the light-emitting element in the pixel is set in a light-emitting state or a non-light-emitting state in each sub-frame period. By dividing one frame into a plurality of sub-frames, the total length of time, in which pixels emit light in one frame period, can be controlled with video signals so that gray scales are displayed.

In the light-emitting display device illustrated in FIG. 14B, in the case where two switching TFTs are arranged in one pixel, the first scanning line driver circuit 5402 generates a signal which is input to a first scanning line serving as a gate wiring of one switching TFT, and the second scanning line driver circuit 5404 generates a signal which is input to a second scanning line serving as a gate wiring of the other switching TFT; however, one scanning line driver circuit may generate both the signals which is input to the first scanning line and the signal which is input to the second scanning line. In addition, for example, there is a possibility that a plurality of scanning lines used for controlling the operation of the switching element are provided in each pixel, depending on the number of the switching TFTs included in one pixel. In that case, one scanning line driver circuit may generate all signals that are input to the plurality of scanning lines, or a plurality of scanning line driver circuits may generate signals that are input to the plurality of scanning lines.

In addition, also in the light-emitting display device, a part of a driver circuit that can include n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistors of the pixel portion. Alternatively, the signal line driver circuit and the scanning line driver circuit can be formed using only the n-channel TFTs described in Embodiment 3.

Moreover, the above-described driver circuit can be used for electronic paper that drives electronic ink using an element electrically connected to a switching element, without being limited to applications to a liquid crystal display device or a light-emitting display device. The electronic paper is also referred to as an electrophoretic display device (electrophoretic display) and has advantages in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.

Electrophoretic displays can have various modes. For example, electrophoretic displays include a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule includes a first particle which is positively charged and a second particle which is negatively charged. In this case, by applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other and only the color of the particles concentrated on one side can be exhibited. Note that the first particle and the second particle each include pigment and do not move without an electric field. Moreover, the colors of the first particle and the second particle are different from each other (including colorless or achroma).

In this way, an electrophoretic display is a display that utilizes a system in which particles are moved by an electric field or the like. An electrophoretic display does not need a polarizer and a counter substrate, which are required in a liquid crystal display device, whereby both the thickness and weight of the electrophoretic display can be reduced remarkably.

A solution obtained by dispersing the aforementioned microcapsules throughout a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by use of a color filter or particles that have a pigment, color display is possible, as well.

When a plurality of microcapsules are arranged over an active matrix substrate and the microcapsules are interposed between an electrode formed over the active matrix substrate and another electrode, an active matrix display device is completed. The active matrix display device can perform display by application of an electric field to the microcapsules. As the active matrix substrate, for example, the active matrix substrate with the use of the thin film transistor obtained in Embodiment 3 can be used.

Note that the first particle and the second particle in the microcapsule may each be formed of a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoretic material or formed of a composite material of any of these.

Through the above process, a highly reliable display device can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with any of the other embodiments as appropriate.

Embodiment 5

In this embodiment, a thin film transistor is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor for a pixel portion and further for a driver circuit. Further, a part or whole of a driver circuit can be formed over the same substrate as a pixel portion, using the thin film transistor according to an embodiment of the present invention, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include, in its category, an element whose luminance is controlled by current or voltage, and specifically include an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel. The display device includes an element substrate corresponding to one mode before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with a means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any of other states.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module to which a connector such as a flexible printed circuit (FPC), tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached; a module having TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

In this embodiment, a liquid crystal display device is shown as an example of a semiconductor device. The appearance and a cross section of a liquid crystal display panel, which is one embodiment of the semiconductor device of the present invention, will be described with reference to FIGS. 22A1 to 22B. FIGS. 22A1 and 22A2 are top views of a panel in which highly reliable thin film transistors 4010 and 4011 each including an In—Ga—Zn—O based non-single-crystal film, and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 22B is a cross-sectional view along line M-N of FIGS. 22A1 and 22A2.

The sealant 4005 is provided so as to surround a pixel portion 4002 and a scanning line driver circuit 4004 which are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are sealed together with liquid crystal 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that the connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 22A1 illustrates an example of mounting the signal line driver circuit 4003 by a COG method, and FIG. 22A2 illustrates an example of mounting the signal line driver circuit 4003 by a TAB method.

The pixel portion 4002 and the scanning line driver circuit 4004 provided over the first substrate 4001 each include a plurality of thin film transistors. FIG. 22B illustrates the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided over the thin film transistors 4010 and 4011.

Each of the thin film transistors 4010 and 4011 corresponds to the highly reliable thin film transistor described in Embodiment 3, in which an In—Ga—Zn—O based non-single-crystal film is included as a semiconductor layer. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with one another corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 respectively which each function as an alignment film, and sandwich the liquid crystal 4008 with the insulating layers 4032 and 4033 interposed therebetween.

Note that the first substrate 4001 and the second substrate 4006 can be formed by using glass, metal (typically, stainless steel), ceramic, or plastic. As an example of plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance between the pixel electrode layer 4030 and the counter electrode layer 4031 (a cell gap). Further, a spherical spacer may also be used. In addition, the counter electrode layer 4031 is electrically connected to a common potential line formed over the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line are electrically connected to each other using a common connecting portion, with conductive particles which are arranged between the pair of substrates interposed therebetween. Note that the conductive particles are included in the sealant 4005.

Alternatively, liquid crystal showing a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, liquid crystal composition in which a chiral agent at 5 wt % or more is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition which includes liquid crystal showing a blue phase and a chiral agent have such characteristics that the response speed is as short as 10 μs to 100 μs, the alignment process is unnecessary because the liquid crystal composition has optical isotropy, and viewing angle dependency is small.

Note that the liquid crystal display device described in this embodiment is an example of a transmissive liquid crystal display device; however, the liquid crystal display device described in this embodiment can be applied to a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

In this embodiment, an example of the liquid crystal display device is described in which a polarizing plate is provided in a position outer than the substrate (on the viewer side) and a coloring layer and the electrode layer used for a display element are provided in a position inner than the substrate; however, the polarizing plate may be provided in an inner position than the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Further, a light-blocking film functioning as a black matrix may be provided.

In this embodiment, the thin film transistor obtained in Embodiment 3 is covered with the insulating layers functioning as a protective layer and a planarization insulating film (the insulating layers 4020 and 4021) so that unevenness of the surface of the thin film transistor is reduced and reliability of the thin film transistor is improved. Note that the protective film is provided to prevent entry of a contaminant impurity such as an organic substance, a metal substance, or moisture included in the air and is preferably a dense film. The protective film can be formed of a single layer or stacked layers formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and/or an aluminum nitride oxide film by a sputtering method. In this embodiment, the protective film is formed by a sputtering method; however, this embodiment is not particularly limited thereto. The protective film may be formed by any of various methods.

Here, the insulating layer 4020 having a stacked-layer structure is formed as the protective film. Here, a silicon oxide film is formed by a sputtering method as a first layer of the insulating layer 4020. The silicon oxide film is used as the protective film, which has an effect to prevent a hillock of an aluminum film used for a source electrode layer and a drain electrode layer.

In addition, an insulating layer is formed as a second layer of the protective film. Here, as a second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. When the silicon nitride film is used as one layer in the protective film, mobile ions of sodium or the like can be prevented from entering a semiconductor region so that variation in electric characteristics of a TFT can be suppressed.

In addition, after forming the protective film, the semiconductor layer may be annealed (at 300° C. to 400° C.).

In addition, the insulating layer 4021 is formed as an insulating film functioning as a planarization film. An organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used for the insulating layer 4021. In addition to such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed from a siloxane-based material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include, as a substituent, an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. In addition, the organic group may include a fluoro group.

There are no particular limitations on formation method of the insulating layer 4021 and any of the following methods can be employed depending on the material of the insulating layer 4021: a CVD method, a sputtering method, an SOG method, spin coating, dipping, spray coating, a droplet discharge method (e.g., an ink-jet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, and the like. When the insulating layer 4021 is formed using a material solution, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time as a baking step of the insulating layer 4021. The baking step of the insulating layer 4021 serves also as the annealing step of the semiconductor layer, and a display device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

In addition, a conductive composition containing a conductive high molecule (also referred to as a conductive polymer) can be used for forming the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed of the conductive composition has preferably a sheet resistance of less than or equal to 1.0×10⁴ Ω/square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule contained in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called π electron conjugated conductive high molecule can be used. As examples thereof, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and a potential are supplied to the signal line driver circuit 4003 which is formed separately, the scanning line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and a terminal electrode 4016 is formed with the same conductive film as the source electrode layers and the drain electrode layers of the thin film transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

Note that FIGS. 22A1 to 22B illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scanning line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scanning line driver circuit may be separately formed and then mounted.

FIG. 23 illustrates an example in which a TFT substrate 2600 is used for a liquid crystal display module which corresponds to one mode of the semiconductor device.

FIG. 23 illustrates an example of a liquid crystal display module, in which the TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the case of the RGB system, coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. A light source includes a cold cathode tube 2610 and a reflective plate 2611, and a circuit substrate 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 through a flexible wiring board 2609 and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.

Through the above process, a highly reliable liquid crystal display device can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with any of the other embodiments as appropriate.

Embodiment 6

In this embodiment, electronic paper is described as an example of a semiconductor device.

FIG. 13 illustrates active matrix electronic paper as an example of a semiconductor device. A thin film transistor 581 used for the semiconductor device can be manufactured in a manner similar to the thin film transistor described in any of Embodiments 1 to 3.

The electronic paper in FIG. 13 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor 581 formed over a substrate 580 is a thin film transistor with a bottom-gate structure, and a source electrode layer or a drain electrode layer is electrically connected to a first electrode layer 587 through a contact hole formed in insulating layers 583, 584, and 585. Between the first electrode layer 587 and a second electrode layer 588, spherical particles 589 each having a black region 590 a and a white region 590 b are provided, which are surrounded by a cavity 594 filled with liquid. A space around the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In FIG. 13, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581. The second electrode layer 588 provided for the substrate 596 and the common potential electrode can be electrically connected to each other using the common connection portion described in the above embodiment, with the conductive particles which are arranged between the pair of substrates interposed therebetween.

Further, instead of the twisting ball, an electrophoretic element can also be used. In this case, a microcapsule having a diameter of approximately 10 μm to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is called electronic paper in general. The electrophoretic display element has higher reflectivity than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through this process, highly reliable electronic paper can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

Embodiment 7

In this embodiment, an example of a light-emitting display device is described as a semiconductor device. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIG. 20 illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. In this example, one pixel includes two n-channel transistors each of which includes an oxide semiconductor layer (an In—Ga—Zn—O based non-single-crystal film) as a channel formation region.

A pixel 6400 includes a switching transistor 6401, a driver transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scanning line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driver transistor 6402. The gate of the driver transistor 6402 is connected to a power supply line 6407 through the capacitor 6403, a first electrode of the driver transistor 6402 is connected to the power supply line 6407, and a second electrode of the driver transistor 6402 is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed over the same substrate. A common connection portion where the common electrode 6408 and the common potential line are connected to each other may be have a structure illustrated in FIG. 1A, FIG. 2A, or FIG. 3A.

The second electrode (common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential with reference to the high power supply potential that is set to the power supply line 6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 and current is supplied to the light-emitting element 6404, so that the light-emitting element 6404 emits light. Here, in order to make the light-emitting element 6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is a forward threshold voltage or higher.

Note that gate capacitance of the driver transistor 6402 may be used as a substitute for the capacitor 6403, so that the capacitor 6403 can be omitted. The gate capacitance of the driver transistor 6402 may be formed between the channel region and the gate electrode.

In the case of a voltage-input voltage driving method, a video signal is input to the gate of the driver transistor 6402 so that the driver transistor 6402 is in either of two states of being sufficiently turned on and turned off. That is, the driver transistor 6402 operates in a linear region. Since the driver transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driver transistor 6402. Note that a voltage higher than or equal to (voltage of the power supply line+Vth of the driver transistor 6402) is applied to the signal line 6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as that in FIG. 20 can be used by changing signal input.

In the case of performing analog grayscale driving, a voltage higher than or equal to (forward voltage of the light-emitting element 6404+Vth of the driver transistor 6402) is applied to the gate of the driver transistor 6402. The forward voltage of the light-emitting element 6404 indicates a voltage at which a desired luminance is obtained, and includes at least a forward threshold voltage. The video signal by which the driver transistor 6402 operates in a saturation region is input, so that current can be supplied to the light-emitting element 6404. In order for the driver transistor 6402 to operate in a saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driver transistor 6402. When an analog video signal is used, it is possible to feed current to the light-emitting element 6404 in accordance with the video signal and perform analog grayscale driving.

Note that the pixel structure illustrated in FIG. 20 is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel illustrated in FIG. 20.

Next, structures of the light-emitting element is described with reference to FIGS. 21A to 21C. A cross-sectional structure of a pixel is described by taking an n-channel driving TFT as an example. Driving TFTs 7001, 7011, and 7021 used for semiconductor devices illustrated in FIGS. 21A to 21C can be manufactured in a manner similar to the thin film transistor described in Embodiment 3 and are highly reliable thin film transistors each including an In—Ga—Zn—O based non-single-crystal film as a semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure, in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure, in which light emission is extracted through the surface on the substrate side; or a dual emission structure, in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. A pixel structure of an embodiment of the present invention can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top emission structure is described with reference to FIG. 21A.

FIG. 21A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is an n-channel TFT and light is emitted from a light-emitting element 7002 to an anode 7005 side. In FIG. 21A, a cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be formed using a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, CaF, MgAg, AlLi, or the like is preferably used. The light-emitting layer 7004 may be formed using a single layer or a plurality of layers stacked. When the light-emitting layer 7004 is formed using a plurality of layers, the light-emitting layer 7004 is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode 7003. It is not necessary to form all of these layers. The anode 7005 is formed using a light-transmitting conductive material such as a film of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The light-emitting element 7002 corresponds to a region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005. In the case of the pixel illustrated in FIG. 21A, light is emitted from the light-emitting element 7002 to the anode 7005 side as indicated by an arrow.

Next, a light-emitting element having a bottom emission structure is described with reference to FIG. 21B. FIG. 21B is a cross-sectional view of a pixel in the case where the driving TFT 7011 is an n-channel transistor and light is emitted from a light-emitting element 7012 to a cathode 7013 side. In FIG. 21B, the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 that is electrically connected to the driving TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. A light-blocking film 7016 for reflecting or blocking light may be formed to cover the anode 7015 when the anode 7015 has a light-transmitting property. For the cathode 7013, a variety of materials can be used as in the case of FIG. 21A as long as they are conductive materials having a low work function. The cathode 7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. Similar to the case of FIG. 21A, the light-emitting layer 7014 may be formed using either a single layer or a plurality of layers stacked. The anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material as in the case of FIG. 21A. As the light-blocking film 7016, a metal or the like that reflects light can be used for example; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can also be used.

The light-emitting element 7012 corresponds to a region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015. In the case of the pixel illustrated in FIG. 21B, light is emitted from the light-emitting element 7012 to the cathode 7013 side as indicated by an arrow.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. 21C. In FIG. 21C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. As in the case of FIG. 21A, the cathode 7023 can be formed using a variety of conductive materials as long as they have a low work function. The cathode 7023 is formed to have a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as the cathode 7023. As in FIG. 21A, the light-emitting layer 7024 may be formed using either a single layer or a plurality of layers stacked. The anode 7025 can be formed using a light-transmitting conductive material as in the case of FIG. 21A.

The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with one another. In the case of the pixel illustrated in FIG. 21C, light is emitted from the light-emitting element 7022 to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that, although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

In this embodiment, the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.

A semiconductor device described in this embodiment is not limited to the structures illustrated in FIGS. 21A to 21C and can be modified in various ways based on the spirit of techniques according to the present invention.

Next, the appearance and the cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of a semiconductor device, are described with reference to FIGS. 24A and 24B. FIG. 24A is a top view of a panel in which highly reliable thin film transistors 4509 and 4510 which are formed over a first substrate 4051 described in Embodiment 3 and each of which includes an In—Ga—Zn—O based non-single-crystal film as a semiconductor layer, and a light-emitting element 4511 are sealed between the first substrate 4510 and a second substrate 4506 with a sealant 4505. FIG. 24B is a cross-sectional view taken along line H-I of FIG. 24A.

A sealant 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503 a and 4503 b, and scanning line driver circuits 4504 a and 4504 b which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scanning line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scanning line driver circuits 4504 a and 4504 b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air as described above.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scanning line driver circuits 4504 a and 4504 b formed over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503 a are illustrated as an example in FIG. 24B.

As each of the thin film transistors 4509 and 4510, the highly reliable thin film transistor described in Embodiment 3, in which an In—Ga—Zn—O based non-single-crystal film is included as a semiconductor layer, can be used. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

Moreover, reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 which is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that a structure of the light-emitting element 4511 is a stacked-layer structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but the present invention is not limited to that described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

A partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 4520 be formed using a photosensitive material and an opening be formed over the first electrode layer 4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 4512 may be formed with a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition wall 4520 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503 a and 4503 b, the scanning line driver circuits 4504 a and 4504 b, or the pixel portion 4502 from FPCs 4518 a and 4518 b.

In this embodiment, a connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511, and a terminal electrode 4516 is formed from the same conductive film as the source and drain electrode layers included in the thin film transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518 a through an anisotropic conductive film 4519.

The second substrate located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for the filler 4507.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scanning line driver circuits 4504 a and 4504 b may be provided as driver circuits formed using a single crystal semiconductor film or polycrystalline semiconductor film over a substrate separately prepared. In addition, only the signal line driver circuits or part thereof, or the scanning line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 24A and 24B.

Through the above process, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with any of the other embodiments as appropriate.

Embodiment 8

A semiconductor device according to the present invention can be applied to electronic paper. Electronic paper can be used for electronic devices of a variety of fields as long as they can display data. For example, electronic paper according to the present invention can be applied to an electronic book (e-book) reader, a poster, an advertisement in a vehicle such as a train, displays of various cards such as a credit card, and the like. Examples of the electronic devices are illustrated in FIGS. 25A and 25B and FIG. 26.

FIG. 25A illustrates a poster 2631 formed using electronic paper. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time. Further, an image can be stably displayed without being distorted. Note that the poster may be configured to transmit and receive data wirelessly.

FIG. 25B illustrates an advertisement 2632 in a vehicle such as a train. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time without a lot of manpower. Further, an image can be stably displayed without being distorted. Note that the advertisement in a vehicle may be configured to transmit and receive data wirelessly.

FIG. 26 illustrates an example of an electronic book reader 2700. For example, the electronic book reader 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are combined with a hinge 2711 so that the electronic book reader 2700 can be opened and closed with the hinge 2711 as an axis. With such a structure, the electronic book reader 2700 can be operated like a paper book.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may be configured to display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, a display portion on the right side (the display portion 2705 in FIG. 26) can display text and a display portion on the left side (the display portion 2707 in FIG. 26) can display graphics.

FIG. 26 illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power switch 2721, operation keys 2723, a speaker 2725, and the like. With the operation keys 2723, pages can be turned. Note that a keyboard, a pointing device, or the like may be provided on the surface of the housing, on which the display portion is provided. Further, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insert portion, or the like may be provided on the back surface or the side surface of the housing. Further, the electronic book reader 2700 may have a function of an electronic dictionary.

The electronic book reader 2700 may be configured to transmit and receive data wirelessly. The structure can be employed in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Embodiment 9

A semiconductor device according to the present invention can be applied to a variety of electronic devices (including an amusement machine). Examples of electronic devices include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 27A illustrates an example of a television set 9600. In the television set 9600, a display portion 9603 is incorporated in a housing 9601. The display portion 9603 can display an image. Further, the housing 9601 is supported by a stand 9605 here.

The television set 9600 can be operated with an operation switch of the housing 9601 or a separate remote controller 9610. Channels and volume can be controlled with operation keys 9609 of the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Further, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Further, when the television set 9600 is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can be performed.

FIG. 27B illustrates an example of a digital photo frame 9700. For example, in the digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display various images. For example, the display portion 9703 can display data of an image taken with a digital camera or the like and function as a normal photo frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame 9700. For example, a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on the display portion 9703.

The digital photo frame 9700 may be configured to transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly to be displayed.

FIG. 28A is a portable game machine and includes two housings, a housing 9881 and a housing 9891, which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine illustrated in FIG. 28A is provided with a speaker portion 9884, a recording medium insert portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, odor, or infrared ray), and a microphone 9889), and the like. Needless to say, the structure of the portable game machine is not limited to that described above. The portable game machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least a semiconductor device according to the present invention is provided. The portable game machine illustrated in FIG. 28A has a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing information with another portable game machine by wireless communication. Note that a function of the portable game machine illustrated in FIG. 28A is not limited to those described above, and the portable game machine can have a variety of functions.

FIG. 28B illustrates an example of a slot machine 9900 which is a large-sized amusement machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 is provided with operation means such as a start lever and a stop switch, a coin slot, a speaker, or the like. Needless to say, the structure of the slot machine 9900 is not limited to the above-described structure. The slot machine may have a structure in which additional accessory equipment is provided as appropriate as long as at least a semiconductor device according to the present invention is provided.

FIG. 29A illustrates an example of a mobile phone handset 1000. The mobile phone handset 1000 is provided with a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

When the display portion 1002 of the mobile phone handset 1000 illustrated in FIG. 29A is touched with a finger or the like, data can be input into the mobile phone handset 1000. Further, operations such as making calls and texting can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode which is a combination of the two modes, that is, a combination of the display mode and the input mode.

For example, in the case of making a call or texting, a text input mode mainly for inputting text is selected for the display portion 1002 so that characters displayed on a screen can be inputted. In that case, it is preferable to display a keyboard or number buttons on almost all area of the screen of the display portion 1002.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the mobile phone handset 1000, display on the screen of the display portion 1002 can be automatically changed by determining the orientation of the mobile phone handset 1000 (whether the mobile phone handset 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

The screen modes are changed by touching the display portion 1002 or using the operation buttons 1003 of the housing 1001. Alternatively, the screen modes may be changed depending on the kind of the image displayed on the display portion 1002. For example, when a signal of an image displayed on the display portion is the one of moving image data, the screen mode is changed to the display mode. When the signal is the one of text data, the screen mode is changed to the input mode.

Further, in the input mode, when input by touching the display portion 1002 is not performed for a certain period while a signal detected by the optical sensor in the display portion 1002 is detected, the screen mode may be controlled so as to be changed from the input mode to the display mode.

The display portion 1002 may function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when the display portion 1002 is touched with a palm or a finger, whereby personal identification can be performed. Further, by providing a backlight or a sensing light source which emits a near-infrared light in the display portion, an image of a finger vein, a palm vein, or the like can be taken.

FIG. 29B also illustrates an example of a mobile phone handset. The mobile phone handset in FIG. 29B includes a display device 9410 and a communication device 9400. The display device 9410 includes a housing 9411 including a display portion 9412 and operation buttons 9413. The communication device 9400 includes a housing 9401 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting portion 9406 which emits light when an incoming call is received. The display device 9410 having a display function can be detached from the communication device 9400 in two directions indicated by arrows. Therefore, the display device 9410 and the communication device 9400 having a telephone function can be attached to each other along either minor axes thereof or major axes thereof. When only the display function is need, the display device 9410 can be used independently while the communication device 9400 is detached from the display device 9410. The communication device 9400 and the display device 9410 each can transmit and receive images or input information by wireless communication or wired communication and each have a rechargeable battery.

Example 1

In this example, results obtained by dry etching of an oxide semiconductor layer and an insulating film with the use of a chlorine gas and an oxygen gas are described.

Samples used in this example are described. As a first oxide semiconductor layer, an In—Ga—Zn—O based non-single-crystal film with a thickness of 150 nm was formed over a glass substrate by a sputtering method. Formation conditions were as follows: the pressure was 0.4 Pa, the power was 500 W, the formation temperature was 25° C., the flow rate of an argon gas was 10 sccm, the flow rate of oxygen was 5 sccm, and a distance between the substrate and a target was 170 mm. The target including In₂O₃, Ga₂O₃, and ZnO at a ratio of 1:1:1 (In:Ga:Zn=1:1:0.5) was used. The composition of the first oxide semiconductor layer obtained by these formation conditions was measured by inductively coupled plasma mass spectrometry (ICP-MS). The result of the measurement was InGa_(0.94)Zn_(0.40)O_(3.31).

Next, as a second oxide semiconductor layer whose conductivity is higher than that of the first oxide semiconductor layer, an In—Ga—Zn—O based non-single-crystal film with a thickness of 150 nm was formed over a glass substrate by a sputtering method. Formation conditions were as follows: the pressure was 0.4 Pa, the power was 500 W, the formation temperature was 25° C., the flow rate of an argon gas was 40 sccm, and a distance between the substrate and a target was 170 mm. The target including In₂O₃, Ga₂O₃, and ZnO at a ratio of 1:1:1 (In:Ga:Zn=1:1:0.5) was used. The composition of the second oxide semiconductor layer obtained by these formation conditions was measured by inductively coupled plasma mass spectrometry. The result of the measurement was InGa_(0.95)Zn_(0.41)O_(3.33).

Next, as an insulating film, a silicon oxynitride film with a thickness of 200 nm was formed over a glass substrate by a CVD method. Formation conditions were as follows: the pressure was 39.99 Pa, the formation temperature was 400° C., the flow rate of silane was 4 sccm, the flow rate of N₂O was 800 sccm, the RF power was 150 W, and a distance between electrodes was 28 mm.

Then, the respective etching rates of the first oxide semiconductor layer, the second oxide semiconductor layer, and the insulating film were measured. The first oxide semiconductor layer, the second oxide semiconductor layer, and the insulating film which had been formed were etched using masks such as photo resists so that each film remains (half etching). After that, the amount of the first oxide semiconductor etched, the amount of the second oxide semiconductor layer etched, and the amount of the insulating film etched were measured by a step-height measurement apparatus, and then, their respective etching rates (nm/min) were calculated from the relation between the amount of the film etched and the time needed for the etching.

The etching was performed by an ICP etching method on the conditions that the ICP power was 1500 W (the size of an electrode: 370 mm×470 mm), the RF bias was 200 W, the pressure was 1.5 Pa, and the substrate temperature was −10° C. In this etching, four different conditions at the different flow rates of a chlorine gas and an oxygen gas which were etching gases were employed (the flow rate of a chlorine gas:the flow rate of an oxygen gas=100 sccm:0 sccm, 85 sccm:15 sccm, 70 sccm:30 sccm, and 55 sccm:45 sccm). The respective etching rates of the conditions were calculated.

The calculation results of the etching rates are shown in FIG. 4. In FIG. 4, a horizontal axis represents the content (volume %) of an oxygen gas in an etching gas (the total of the chlorine gas and the oxygen gas), a vertical axis on the left side represents an etching rate (nm/min), and a vertical axis on the right side represents a selectivity. In addition, in FIG. 4, a circle represents the etching rate of the first oxide semiconductor layer, a triangle represents the etching rate of the second oxide semiconductor layer, a square represents the etching rate of the insulating film, and a cross represents the selectivity. Note that the selectivity shown in FIG. 4 is the etching rate of the first oxide semiconductor layer with respect to the etching rate of the insulating film.

From the results shown in FIG. 4, a significant difference in the etching rate between the first oxide semiconductor layer and the second oxide semiconductor layer was not observed even though the content (volume %) of the oxygen gas in the etching gas was increased. On the other hand, the results showed that the etching rate of the insulating film was decreased when the content (volume %) of the oxygen gas in the etching gas was increased. In particular, the results showed that when the content of the oxygen gas in the etching gas is 15 volume % or more, the etching rate of the insulating film was decreased.

In addition, it was understood that the selectivity of the first oxide semiconductor layer with respect to the insulating film (a ratio of the etching rate of the first oxide semiconductor layer with respect to the etching rate of the insulating film) was determined, which showed that the selectivity was increased to 4.2 at the maximum with addition of oxygen to the etching gas although the etching rate was less than 1 without addition of oxygen to the etching gas as shown in FIG. 4. Further, a significant difference in the etching rate between the first oxide semiconductor layer and the second oxide semiconductor layer is not observed. Therefore, as for the selectivity of the second oxide semiconductor layer with respect to the insulating film, the result similar to the result relating to the selectivity of the first oxide semiconductor layer with respect to the insulating film is obtained.

As described above, it was understood that when the rate of an oxygen gas added in the etching gas was increased, the etching rate of the insulating film was able to be smaller than those of the first oxide semiconductor layer and the second oxide semiconductor layer. In addition, it was understood that when the content of an oxygen gas in the etching gas was 15 volume % or more, each selectivity of the first oxide semiconductor layer and the second oxide semiconductor layer with respect to the insulating film was able to be increased. In this manner, by inclusion of an oxygen gas in the etching gas, the selectivity of the oxide semiconductor layer with respect to the insulating film can be increased. Accordingly, when part of an oxide semiconductor layer formed over an insulating film (the part near the surface of the oxide semiconductor layer) is removed (channel-etched), damage to exposed part of the insulating film can be suppressed.

This application is based on Japanese Patent Application serial no. 2008-271598 filed with Japan Patent Office on Oct. 22, 2008, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a transistor; a terminal portion; a first copper layer and a second copper layer; a first insulating layer over the first copper layer and the second copper layer; an oxide semiconductor film over the first insulating layer; a third copper layer and a fourth copper layer over the first insulating layer; a second insulating layer over the oxide semiconductor film, the third copper layer and the fourth copper layer; and a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent, wherein the third copper layer is electrically connected to the oxide semiconductor film, wherein the oxide semiconductor film comprises a channel region of the transistor, wherein the first copper layer comprises a gate electrode of the transistor, wherein the fourth copper layer is directly in contact with the second copper layer through a first contact hole of the first insulating layer, wherein the pixel electrode is electrically connected to the third copper layer, wherein the electrode is electrically connected to the second copper layer through the fourth copper layer, and wherein the terminal portion comprises the second copper layer, the fourth copper layer, and the electrode.
 2. The semiconductor device according to claim 1, wherein the electrode is electrically connected to the fourth copper layer through a second contact hole of the second insulating layer, wherein a location of the first contact hole is different from a location of the second contact hole.
 3. The semiconductor device according to claim 1, wherein the third copper layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.
 4. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is over the first semiconductor layer and is stacked on the first semiconductor layer.
 5. The semiconductor device according to claim 4, wherein the second semiconductor layer is not stacked on the first semiconductor layer on the channel region.
 6. The semiconductor device according to claim 1, wherein the first insulating layer comprises aluminum or tantalum.
 7. The semiconductor device according to claim 1, wherein the second insulating layer comprises aluminum or tantalum.
 8. A semiconductor device comprising: a transistor; a terminal portion; a first copper layer and a second copper layer; a first insulating layer over the first copper layer and the second copper layer; an oxide semiconductor film over the first insulating layer; a third copper layer and a fourth copper layer over the first insulating layer; a second insulating layer over the oxide semiconductor film, the third copper layer and the fourth copper layer; and a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent, wherein the third copper layer is electrically connected to the oxide semiconductor film, wherein the oxide semiconductor film comprises a channel region of the transistor, wherein the oxide semiconductor film comprises a region overlapping the third copper layer, wherein a thickness of the channel region is thinner than the region, wherein the first copper layer comprises a gate electrode of the transistor, wherein the fourth copper layer is directly in contact with the second copper layer through a first contact hole of the first insulating layer, wherein the pixel electrode is electrically connected to the third copper layer, wherein the electrode is electrically connected to the second copper layer through the fourth copper layer, and wherein the terminal portion comprises the second copper layer, the fourth copper layer, and the electrode.
 9. The semiconductor device according to claim 8, wherein the third copper layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.
 10. The semiconductor device according to claim 8, wherein the oxide semiconductor film comprises a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is over the first semiconductor layer and is stacked on the first semiconductor layer.
 11. The semiconductor device according to claim 10, wherein the second semiconductor layer is not stacked on the first semiconductor layer on the channel region.
 12. The semiconductor device according to claim 8, wherein the first insulating layer comprises aluminum or tantalum.
 13. The semiconductor device according to claim 8, wherein the second insulating layer comprises aluminum or tantalum.
 14. A semiconductor device comprising: a transistor; a terminal portion; a first copper layer and a second copper layer; a first insulating layer over the first copper layer and the second copper layer; an oxide semiconductor film over the first insulating layer; a third copper layer and a fourth copper layer over the first insulating layer; a second insulating layer over the oxide semiconductor film, the third copper layer and the fourth copper layer; and a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent, wherein the third copper layer is electrically connected to the oxide semiconductor film, wherein the oxide semiconductor film comprises a channel region of the transistor, wherein the oxide semiconductor film comprises a region overlapping the third copper layer, wherein a thickness of the channel region is thinner than the region, wherein the second insulating layer is directly in contact with the channel region, wherein the first copper layer comprises a gate electrode of the transistor, wherein the fourth copper layer is directly in contact with the second copper layer through a first contact hole of the first insulating layer, wherein the pixel electrode is electrically connected to the third copper layer, wherein the electrode is electrically connected to the second copper layer through the fourth copper layer, and wherein the terminal portion comprises the second copper layer, the fourth copper layer, and the electrode.
 15. The semiconductor device according to claim 14, wherein the electrode is electrically connected to the fourth copper layer through a second contact hole of the second insulating layer, wherein a location of the first contact hole is different from a location of the second contact hole.
 16. The semiconductor device according to claim 14, wherein the oxide semiconductor film comprises a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is over the first semiconductor layer and is stacked on the first semiconductor layer.
 17. The semiconductor device according to claim 16, wherein the second semiconductor layer is not stacked on the first semiconductor layer on the channel region.
 18. The semiconductor device according to claim 14, wherein the first insulating layer comprises aluminum or tantalum.
 19. The semiconductor device according to claim 14, wherein the second insulating layer comprises aluminum or tantalum. 